1. Field of the Invention
The present invention is directed in general to the field of semiconductor devices. In one aspect, the present invention relates to the use of die level metal tiling or dummy features to improve structural integrity of an integrated circuit.
2. Description of the Related Art
The use of conductive balls, such as solder balls, to make electrical connection to a bond pad is a known method to make electrical connection to electrical circuitry of a semiconductor die. Conductive ball packaging is one type of semiconductor packaging known in the industry as flip chip interconnection. As geometries in semiconductors continue to shrink in size due to improvements in the technology for making semiconductors, the sizes of bond pad regions have become smaller, resulting in increased stress to the bond pad structure when physical connection is made to the semiconductor die. Additional mechanical integrity problems are created by the interconnect structures used with the manufacturing smaller geometry semiconductors. For example, bond pad structures fabricated with copper interconnect metallization and low dielectric constant (low-k) dielectrics are susceptible to mechanical damage during the bonding process, due to the lower Young's modulus and lower fracture toughness of such materials. As a result, the underlying stack of metal and dielectric layers in such bond pad structures may mechanically fracture or delaminate more easily or otherwise be subject to package to die mismatch stresses (such as generated during die attach process) resulting in package level die failures.
Conventional approaches for addressing the structural integrity problems have increased the metal tiling density only in the region beneath the flip chip bond pads. Other approaches used in die with ultra low-k (ULK) dielectrics have required exclusion of ULK from the upper layers of the interconnect stack to meet package requirements, or have required replacement of the ULK with TEOS in the case of copper padless designs where last metal wiring is selectively connected to the bump metallurgy. As a result, prior methods of generating tiling under and near the pads do not provide the optimal density, spacing and positioning of tiles over a whole die, or otherwise result in die having reduced or diminished performance or increased fabrication costs.
Accordingly, there is a need for improved semiconductor processes and devices having advanced circuit interconnects in the die that use low modulus, low hardness, and low dielectric constant materials that can meet package toughness requirements with minimum interference with die design. There is also a need for a flip chip fabrication process which improves the die reliability in reflow and package environments by optimizing metal tiling density across the entire die. In addition, there is a need for a semiconductor manufacturing process and design which overcomes the problems in the art, such as outlined above. Further limitations and disadvantages of conventional processes and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for purposes of promoting and improving clarity and understanding. Further, where considered appropriate, reference numerals have been repeated among the drawings to represent corresponding or analogous elements.